A Low Area Fully Pipelined Implementation of JPEG on FPGA

Authors : Atakan DOĞAN, İsmail SAN

Pages : 685-697

View : 12 | Download : 7

Publication Date : 2018-09-01

Article Type : Research Paper

Abstract :This paper presents a low-area and high-throughput design and implementation of JPEG encoder on FPGA. The design consists of three main components: insert ignore into journalissuearticles values(1); 2-D DCT module, based on the row-column decomposition technique, insert ignore into journalissuearticles values(2); Quantization in zigzag ordering, based on look-up tables, and insert ignore into journalissuearticles values(3); Entropy coder, transforming the quantized DCT coefficients into JPEG words. All components are fully pipelined and optimized for FPGA resource utilization. The proposed implementation of JPEG encoder is able to encode 143 and 71 SDTV frames per second with 720x480 gray scale and color pixels per frame, respectively, on Xilinx Spartan 6 FPGA. Moreover, the proposed architecture is capable of encoding at least 53 and 26 HD Ready TV frames per second with 1280x720 gray scale and color pixels per frame, respectively, on this FPGA chip. Thus, the proposed JPEG encoder architecture is well-suited to various image and video compressing applications where performance and area are significantly important.
Keywords : JPEG compression, Discrete cosine transform, Logic design, FPGA