Design and implementation of Area and Power efficient reconfigurable FIR filter with low complexity coefficients

Authors : Sridevi SRİADİBHATLA, Killadi BABOJİ

Pages : 494-507

View : 11 | Download : 4

Publication Date : 2019-06-01

Article Type : Research Paper

Abstract :This paper presents the design and implementation of area and power efficient reconfigurable finite impulse response insert ignore into journalissuearticles values(FIR); filter. We present a method for designing a reconfigurable filter with low binary complexity coefficients insert ignore into journalissuearticles values(LBCC); and thus to optimize the filter while satisfying the design specifications. The total number of non zero binary bits is taken as a measure of the binary complexity insert ignore into journalissuearticles values(BC); of a coefficient. We propose two implementation architectures namely signed-magnitude architecture insert ignore into journalissuearticles values(SMA); and signed-decimal architecture insert ignore into journalissuearticles values(SDA); which are based on 3-bit binary common sub expression elimination insert ignore into journalissuearticles values(BCSE); algorithm and vertical horizontal BCSE insert ignore into journalissuearticles values(VHBCSE); algorithm respectively. SMA and SDA reduce the redundant computations of the coefficient multiplications in the filter. The proposed filters are synthesized on tsmc 65nm CMOS technology. The synthesis results show that the proposed filters are area and power efficient when compared with the existing ones.
Keywords : Reconfigurable FIR filter, BCSE algorithm, VHBCSE algorithm, Binary complexity