Energy savings in simultaneous multi-threaded processors through dynamic resizing of datapath resources

Authors : Gürhan KÜÇÜK, Mine MESTA

Pages : 125-139

View : 16 | Download : 7

Publication Date : 0000-00-00

Article Type : Research Paper

Abstract :Nowadays, all the designers of systems from high-performance servers to battery-operated handheld devices aim for reliability, high-performance and longevity. Central within these aims the issue of processor power consumption is becoming increasingly important. In this study, we aim to adapt our already-proven method for single-threaded superscalar processors to simultaneous multi-threaded insert ignore into journalissuearticles values(SMT); processors for energy savings. The original method focused on resizing datapath resources according to the demands of running applications. To achieve this, the targeted resources are physically divided into multiple partitions, and turned on and off according to the needs of the applications. Since, the energy consumption of the turned-off datapath resources is quite low, as a result, it becomes possible to have great amount of energy savings within a processor. However, special care must be taken when there are multiple threads racing against each other to gain access to shared datapath resources. As a result, our proposed microarchitectural technique achieves 0.5% Instructions Per Cycle insert ignore into journalissuearticles values(IPC); and 3.2% Total number of instructions Per Cycle insert ignore into journalissuearticles values(TPC); improvement, while it turns off 45% of the Reorder Buffer insert ignore into journalissuearticles values(ROB);, 59% of the Load-Store Queue insert ignore into journalissuearticles values(LSQ);, 43% of the Issue Queue insert ignore into journalissuearticles values(IQ);, 30% of the integer Physical Register Files insert ignore into journalissuearticles values(PRF); and, finally, 48% of the floating PRF, on the average across all simulated benchmarks. According to our estimates, the total processor power is reduced by 12%, on the average.
Keywords : Microarchitectural techniques, energy reduction, simultaneous multi threaded processors