LOW-POWER DYNAMIC COMPARATOR WITH HIGH PRECISION FOR SAR ADC

Authors : Ersin ALAYBEYOĞLU

Pages : 85-91

Doi:10.31127/tuje.625475

View : 8 | Download : 7

Publication Date : 2020-04-01

Article Type : Research Paper

Abstract :In this work, low-power dynamic comparator is presented with auto-zeroing technique for successive approximation register insert ignore into journalissuearticles values(SAR); analogue-to-digital converter insert ignore into journalissuearticles values(ADC);. The comparator designed with DTMOS technique operates in subthreshold region. The designed circuit consumes low power with high gain. The dynamic range of the comparator is increased with a new biasing technique for DTMOS transistors. The core design consumes 6.01µW power and overall design consumes 17.06µW. The design is realized with two different supply voltage with 600mV insert ignore into journalissuearticles values(core design); and 1.8V insert ignore into journalissuearticles values(biasing circuit);. The comparator has been simulated with 0.18µm TSMC process in Cadence environment. 
Keywords : SAR ADC, Comparator, CMOS analog integrated circuits